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LT3760
APPLICATIONS INFORMATION
Thermal Considerations
The internal power dissipation of the LT3760 comes from 3
main sources: V IN quiescent current (I Q total), V IN current
for GATE switching (I GATE ) and the LT3760 LED current
sources. Since the maximum operational V IN voltage is
40V, care should be taken when selecting the switching
frequency and type of external power MOSFET since the
current required from V IN for GATE switching is given by,
I GATE = f OSC ? Qg
where Q g is the gate charge (at V GS = INTV CC ) specified
for the MOSFET and f OSC is the programmed switching
frequency for the LT3760. A low Q g MOSFET should al-
ways be used when operating the LT3760 from high V IN
voltages. The internal junction temperature of the LT3760
can be estimated as:
T J = T A + [V IN ? ( I QTOTAL + (f OSC ? Q g )) + (8 ? I(LED X ) ? 1.1 V)]
? θ JA
where, T A is the ambient temperature for the LT3760
I QTOTAL represents the V IN quiescent current for the LT3760
(not switching, PWM = 1.5V and CTRL = 0.1V) - illustrated
in the Typical Characteristics Graphs – plus the base cur-
rents of active channels (typically 8 ? I(LED)/75). θ JA is
the thermal resistance of the package (28°C/W for the
28-pin TSSOP package).
Example : For a 12W LED driver application requiring 8
strings of 10 LEDs each driven with 40mA, V IN = 24V, f OSC
= 1MHz, Q g (at 7V V GS ) = 15nC, I(LED X ) = 40mA, and an
85°C ambient temperature for the LT3760 IC, the LT3760
junction temperature can be approximated as:
T J = 85°C + [24 ? (9.5 mA + (8 ? 40mA/75) + (1MHz
? 15 nC )) + (8 ? 40 mA ? 1.1 V )] ? 34
= 85°C + [(24 ? 28.8 mA) + (320mA ? 1.1 V )] ? 34
= 85°C + (0.691W + 0.35W ) ? 34
= 85°C + 35°C
The exposed pad on the bottom of the package must be
soldered to the ground plane. The ground plane should
be connected to an internal copper ground plane with vias
placed directly under the package to spread out the heat
generated by the LT3760.
Circuit Layout Considerations
As with all switching regulators, careful attention must
be given to PCB layout and component placement to
achieve optimal thermal, electrical and noise performance.
The exposed pad of the LT3760 should be soldered to a
continuous copper ground plane underneath the device
to reduce die temperature and maximize the power capa-
bility of the IC. The signal ground (GND, pin 24) is down
bonded to the exposed pad near the RT and V C pins.
I SET , R T and V C components should be connected to an
area of ground copper connected to pin 24. The OVP SET
track should be kept away from fast moving signals and
not loaded with an external capacitor. GATE pin turn off
currents escape through a downbond to the exposed pad
and exit the PGND, pin 10. This area of copper and pin
10 should be the power ground (PGND) connection for
the inductor input capacitor, INTV CC capacitor and output
capacitor. A separate bypass capacitor for the V IN pin of
the IC may be required close the V IN pin and connected to
the copper area associated with signal ground, pin 24. To
minimize MOSFET peak current sensing errors the sense
resistor (RS) should have Kelvin connections to the SENSE
pin and the power ground copper area near the pin. The
MOSFET drain rise and fall times are designed to be as
short as possible for maximum efficiency. To reduce the
effects of both radiated and conducted noise, the area of
the copper trace for the MOSFET drain should be kept as
small as possible. Use a ground plane under the switching
regulator to minimize interplane coupling. The Schottky
diode and output capacitor should be placed as close as
possible to the drain node to minimize this high switching
frequency path.
T J = 120°C
3760fc
21
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